A high-speed link is a point-to-point interconnect that transfers data between two components using a link transfer protocol. Using high-speed differential signaling and sophisticated clocking, links are replacing buses as the main interconnect between different components (such as, a processor, a chipset, an input/output bridge, etc.) within a computer system. Links make use of a link transfer protocol that is different from a bus transfer protocol. For example, in the case of the link transfer protocol, transactions in links are broken up into requests and replies to increase scalability and to hide transfer latency.
Component functional tests have proven to be valuable in detecting fault types that are not easily modeled or excited with structural tests. One requirement to enable component functioning tests is the availability of cycle-accurate boundary (interface) traces for a device under test (DUT). According to existing techniques for performing component functional tests, simulation traces (boundary/interface behavior) for a (DUT) are captured during simulation. These simulation traces are then stored in a memory of an automatic test equipment (ATE), and later injected into the (DUT). The (DUT's) responses to the simulation traces can then be compared to an expected response. A prerequisite to this manner of functional testing is the existence of full count, high performance ATE's that match the behavior of the DUT's buses.
Recent advances in semiconductor technology has led to the development of devices and interfaces that operate at frequencies ranging up to several Gigahertz. These high-speed/frequency devices are also paired with high bandwidth data transfer input/output (IO) channels to provide a higher level of system level performance. To support these high bandwidth IO, link based architectures replace traditional bus structures. Link based architectures feature low voltage differential, clock embedded signaling technologies and require very unique complementary circuits to read/write the data sent off the IO channels. These developments in processors, IO speeds, and signaling technologies are placing unique challenges on ATE's. For example, existing ATE's do not have the speed or the number of IO channels or the signaling technologies to perform functional testing of components, as described.
One solution to this problem is to perform a true-system test, i.e., where the component, its operating system and any loaded applications are tested. However, a system test is usually done for a single system/design, selected operating systems and selected applications. Further, only a few selected functions/aspects of the selected operating systems and applications are tested. Thus, the number of faults that can be excited is limited.
Structure based functional tests (SBFT) and functional random instruction tests for speed (FRITS) are execution-based test methodologies designed to address the ATE's speed and input/output bandwidth issues. Under SBFT's and FRITS' methodologies, a test code is first loaded into a DUT's internal storage, for example, the caches in a processor. Thereafter, the test code is executed and is used to test different parts of the DUT. Because all testing is done internally, the ATE is effectively decoupled from component testing, thus solving the ATE's speed and I/O bandwidth and signaling problems. One drawback with this type of testing is that it does not cover the DUT's input/output channels as well as the associated protocol, crossbar and link control layers. In order to extend SBFT and FRITS's type tests to cover a DUT's input/output channel and all these other associated logic, ATE's will be required to provide the proper IO responses at the right time. However, this approach would be limited by the ATE's speed, IO bandwidth and signaling complexity problems.